This invention is in the field of analog circuit design, and is more specifically directed to the modeling of the performance of analog circuits.
Performance modeling has become an important process in the design and manufacture of integrated circuits, both of the digital and analog type. As is fundamental in the art, the realization of an electronic circuit design requires the definition of the layout of the circuit, as physically-realizable devices, according to a selected set of design rules and manufacturing process parameters. Of course, the actual manufacture of the designed circuit will involve variations in the manufacturing process from nominal values in the design, and these variations will affect the eventual performance of the manufactured device. Performance modeling refers to a modeling or simulation technique in which the performance of the designed circuit may be modeled over the set of variations in the process parameters. This modeling can be used to determine the worst case circuit performance that can be expected from a given manufacturing process, to ensure that the circuit, as it will be manufactured, will need product specifications and design goals. Additionally, one may use the results of the modeling to determine the sensitivity of circuit performance to various process parameters.
Conventional performance modeling techniques to derive worst case simulations in digital circuits are generally based upon estimators that relate combinations of process parameters (referred to as “ vectors”) to the worst case performance measurements of digital gate delays and current drawn. In one conventional approach, worst case performance is derived by simulation of the circuit at each “corner” in the process parameter space, where each corner corresponds to a combination of extremes of the parameters. Of course, as the number of process parameters becomes even somewhat large, the number of “corners” at which simulation is required explodes to a prohibitively high number.
According to another approach, worst case vectors are heuristically determined, based on the observed effects of process and environmental parameters upon delay and current in digital circuits, from which the best case and worst case vectors are determined for the delay and current performance parameters. Models resulting from these vectors are also known as the “weak” and “strong” models. However, current trends of smaller device sizes and lower power supply voltage have greatly reduced the accuracy of historically valid vectors when applied to modern circuits.
A recent approach toward producing valid worst case vectors for digital circuits is based upon a quasi-empirical approach, in which a set of circuits such as inverter chains, ring oscillators, and the like are identified as “Figure of Merit” (FOM) circuits. The circuit designers determine the desired performance from the FOM circuits, extrapolating the determined performance to the overall performance of the larger-scale circuit under design. Statistical models for the corresponding manufacturing process are then applied to the FOM circuits by way of a Monte Carlo experiment, to provide the endpoints of the performance distribution over the process variations. The historically-used worst case vectors are then applied to a Design of Experiment (“DoE”) exercise around the worst case vectors, to derive the DoE point most closely corresponding to the upper and lower bounds of the performance distribution from the Monte Carlo experiment. The DoE vectors are then magnified (i.e., multiplied) so that the Monte Carlo performance values fall within the range of the magnified DoE vectors.
This recent approach has provided, in some cases, a reasonable set of worst case vectors for digital circuits. However, because the initial guess used for the DoE is somewhat arbitrary, the resulting model has somewhat limited applicability over manufacturing processes, requiring the generation of the worst case vectors for each manufacturing process flow. It has also been observed that the magnifying of the DoE results causes the inclusion of points, in process space, that would not otherwise be included (i.e., points that do not have a statistically significant likelihood of actually occurring); further, the worst case vectors have been observed to overpredict the range of performance of several circuit topologies. Automation of this approach is also somewhat limited, considering that the application of the historical worst case vector and also the selection of the FOM circuits is somewhat intuitive, thus requiring input from human experts.
Last, but not least, this conventional approach does not translate well to analog circuits. As is known in the art, digital circuits, and particularly the performance parameters of delay and current drawn, vary with process variations in a relatively well-behaved manner. In this regard, worst case process extremes generally translate to worst case performance extremes. This predictable behavior is the basis of the selection of the historically-valid vectors or the DoE starting point. However, it has been observed, in connection with the present invention, that such predictable behavior often does not apply to analog circuits. For example, a worst case vector of an analog circuit may correspond to the combination of several process parameters, none of which are at their process variation extreme. As a result, the generation of worst case vectors for analog circuits, particularly those formed according to state-of-the-art manufacturing process es and design rules, has become difficult if not impossible using conventional worst case modeling techniques.